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	A Parallel Synchronous Model of Computation for Embedded Software

Host: Dr. Francesco Regazzoni

Monday

25.03

USI Lugano Campus, room SI-007, Informatics building

11:30-12:30


	Patrick Schaumont Virginia Tech, USA

Abstract
Synchronous models of computation express computations as discrete steps. Synchronous models of computation produce deterministic results, and this makes them well suited for control software, and synchronous digital hardware. However, synchronous models of computation do not easily scale to larger designs. While Globally Asynchronous, Locally Synchronous (GALS) methods solve some of the scaling issues of synchronous models, they also lose the critical benefits of synchronous design, namely the determinism and the static properties.
We propose a system modeling technique that enables parallel operation of a synchronous paradigm in software. We treat an n-bit processor as n parallel 1-bit processors, each concurrently running the same synchronous bit-program. Each of these programs is synchronous with the other copies. However, each program is still capable of independent control flow. To achieve this, we model the synchronous bit-program as an FSMD (Finite State Machine with Datapath) within a bitslice of the processor. On an n-bit processor, there are n parallel FSMD.
We describe original applications of the proposed parallel synchronous model of computation, such as automatic fault detection on commodity processors and variable-precision processing.

Biography
Patrick Schaumont is a Professor in Computer Engineering at Virginia Tech. His research interests are in design and design methods of secure, efficient and real-time embedded computing systems. He received the Ph.D. degree in Electrical Engineering from UCLA in 2004 and the MS degree in Computer Science from Ghent University in 1990. He served as program co-chair for several conferences in cryptographic and secure engineering, including CHES and HOST. He received the National Science Foundation CAREER Award in 2007.