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Exploring Parallelism for Domain-Specific Acceleration in Heterogeneous Systems - AR/VR, Molecular Dynamics Acceleration
Host: Prof. Fernando Pedone
Computational time and energy consumption in computer systems do not come for free. The breakdown of Dennard scaling, and the seemingly inescapable end of Moore’s law economic aspect, have presented new challenges to the computer architects, striving to achieve increased performance in the modern computing systems. Heterogeneous Computing emerges as a solution to address these issues, however the complexity of the designs of heterogeneous systems, consisting of software processors, GPUs and/or hardware accelerators, has also raised dramatically. To address these issues we propose a set of automated tools that can aid the design process by selecting high performance HW/SW designs, while minimizing the cost in terms of hardware resources and/or energy. These tools can identify and select good HW acceleration candidates, suggest optimizations to be implemented, expose parallelism in applications and target them to specific platforms that may vary in HW area resources budget, micro-architecture characteristics and memory hierarchy.
Under the scope of this talk I will be focusing on methods that automatically expose multi-level parallelism from the Intermediate Representation of applications in order to exploit parallelism in HW acceleration, targeting the acceleration of a specific domain of accelerators, such as Augmented Reality/ Virtual Reality (AR/VR). These methods can be extended to target other families of demanding and lengthy simulations, such as the ones running Molecular Dynamics (MD). Such a tool-chain, parts of it still under development, would push the boundaries of the state-of-the-art and provide heterogeneous designs that can incorporate software CPUs, GPUs and HW accelerators, offloading demanding parts of the computation to GPUs and HW accelerators, while accounting for memory latency and platform characteristics, in order to offer increased performance and minimize hardware resources and energy requirements.
Georgios Zacharopoulos was born and raised in Athens, where he received his BSc degree from University of Piraeus in 2012. He received his MSc degree in Computer Science from Uppsala University, Uppsala, Sweden in 2015. His Master Thesis was included in a paper he co-authored, that received the Best Paper Award in the 25th International Conference on Compiler Construction (CC). He completed his PhD at Università della Svizzera Italiana, Lugano, Switzerland in 2020, during which he carried out a research visit in Columbia University, NYC in 2018. From March 2020 he is a Postdoctoral Researcher in Harvard University, where he continues his research investigating methods based on compiler analysis (e.g. LLVM, Polly) and machine learning, to automate the HW/SW partitioning and optimization phases of heterogeneous computing platforms.
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